Write a VHDL program to create an n-bit register with the following specificatio

Question

Write a VHDL program to create an n-bit register with the following specifications. Please answer the question in exactly the manner it is stated, otherwise the solution is not helpful

The input signals must be...

1) select 2) clock 3) enable_out 4) date_in

The output signal is data_out

The enable_out signal enables the contents of the register to be placed on the data_out bus. If enable_out is 0 then the register is disconnected from the data_out bus (high impedance).

The data_in and data_out busses are of size n.

The select lines control the register operations. The register must perform the following operations, which are all synchronous with the clock. These operations are performed regardless of the value of enable_out.

Operations 1)load 2) shift_left 3)shift_right 4) rotate_left 5) rotate_right

To accomplish this you should create a new data type that can have the following 5 values

Values: 1) Load 2) shift_left 3) shift_right 4)rotate_left 5) rotate_right

The select input should be a signal of the data type you create.

To accomplish this task you should create two VHDL files

1) a file that is a package which contains the new data type you created

2) the file with the multifunction register code. (In the entity the select input can be listed as having the data type you created in your package).

The architecture should have one process that will generate the flip-flops (i.e. a registered process). In that same process you should use a case statement that implements the five different operations.

Note: Do not use bit as a data type, instead use STD_LOGIC

Explanation / Answer

library ieee; use ieee.std_logic_1164.all; entity SReg is generic ( n : integer := 4); port( clk: in std_logic; reset: in std_logic; enable: in std_logic; --enables shifting parallel_in: in std_logic_vector(n-1 downto 0); s_in: in std_logic; --serial input s_out: out std_logic --serial output ); end SReg; architecture behavioral of SReg is signal temp_reg: std_logic_vector(n-1 downto 0) := (Others => '0'); TYPE POSSIBLE_STATES IS (waiting, shifting); signal state : POSSIBLE_STATES; begin accum

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