Please show all your work Hroblem 2: write a verilog counter code that counts in

Question

Please show all your work Hroblem 2: write a verilog counter code that counts in both the up and down directions. The preset is to be set to decimal value 3. That is, upon asserting the reset signal low, the register value should be reset to 3. Also, upon asserting the load signal LD, the register value should be set to the input value DIN. Both the reset and the load are synchronous and the module should count on the rising edge of the clock. The following are the ports of the module: 1-bit clock input, all actions performed on rising edge 1-bit preset (synchronous) then count down) edge 1-bit input (if '1', then count up, o, rising 1-bit load enable input, loads synchronized with cLK RESET N UP DNN 3-bit input data for loading counter value DIN 3-bit result

Explanation / Answer

module Up_down_counter(
input CLK,
input RESET_N,
input UP_DNN,
input LD1,
input [2:0] DIN,
output [2:0] Q
);

reg [2:0] out;

always @(posedge clk)
if (reset) begin // active high reset
out <= 2'b0 ;
end
else if (LD1) begin
out <=DIN ;
end
else if (UP_DNN) begin
out <= out + 1;
end
else begin
out <= out - 1;
end
assign Q=out;
endmodule

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