1. Given the circuit in Figure 1, each two-input XOR gate has a propagation dela

Question

1. Given the circuit in Figure 1, each two-input XOR gate has a propagation delay of 60 ps and a contamination delay of 40 ps.

Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q propagation delay of 70 ps, and a clock-to-Q contamination delay of 50 ps.

(a) If there is no clock skew, what is the maximum operating frequency of the circuit?

1. Given the circuit in Figure 1, each two-input XOR gate has a propagation delay of 60 ps and a contamination delay of 40 ps. Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q propagation delay of 70 ps, and a clock-to-Q contamination delay of 50 ps. (a) If there is no clock skew, what is the maximum operating frequency of the circuit? (b) How much clock skew can the circuit tolerate before it might experience a hold time violation xOR XOR XOR XOR XOR XOR CLK CLK CLK Figure 1: a sequential circuit with 11 Flip-Flops and 7 XOR gates

Explanation / Answer

a) Clock Period Tc = Tcq + Tpd + Tsu   ; If there is no clock skew

Where Tcq is clock-to-Q propagation delay

Tpd is propagation delayof XOR

Tsu is setup time of flip flop

For the given circuit,  Clock-to-Q propagation delay of the flip flop Tcq = 70ps

Propagation delay Tpd = 5 * 60ps = 300ps ; (As in the longest path, there will be 5 XOR gate)

Setup time Tsu = 60ps

So, Tc = 70 + 300 + 60 = 430ps

Therefore, Maximum clock frequency fc = 1/Tc = 2.33 GHz

b) Tcq+ Tcd = Th + Tskew ; Where Tcd is contamination delay of XOR

70ps + 40ps = 20ps + Tskew

Tskew = 90ps

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