(a) A half adder is a circuit that can add two bits at a time to produce a sum a
ID: 1716401 • Letter: #
Question
(a) A half adder is a circuit that can add two bits at a time to produce a sum and a
carry. Design a half adder using only two gates. Write an entity-architecture pair
to implement the half adder. Now write an entity-architecture pair to implement
a full adder using two instances of your half adder and an OR gate. Use the port
definitions specified below:
For the half adder: port (a, b: in bit; s, c: out bit);
For the full adder: port (a, b, cin: in bit; sum, cout: out bit);
(b) Simulate your code and test it using the following inputs:
a b cin = 0 0 1, 0 1 1, 1 1 1, 1 1 0, 1 0 0
How would I do this problem when writing it in VHDL?
Explanation / Answer
half adder code:
library ieee;
use ieee.std_logic_1164.all;
entity hf is
port (a,b:in bit;
sum,carry:out bit);
end hf;
architecture str of hf is
begin
sum<= a xor b;
carry<= a and b;
end str;
full adder:
library ieee;
use ieee.std_logic_1164.all;
entity fulladderstructural is
port (x,y,cin:in bit;
fsum,fcarry:out bit);
end fulladderstructural;
architecture structural of fulladderstructural is
component halfadder
port (a,b:in bit;
sum,carry:out bit);
end component;
signal s1,c1,c2,h,g: bit;
begin
h1: halfadder port map (x,y,s1,c1);
h2: halfadder port map (s1,cin,fsum,c2);
h <= cin and x;
g <= cin and y;
fcarry <= c1 or h or g;
end structural;
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