16-bit incrementer, and 8-bit multiplier. You can use below entity declaration f
ID: 1716934 • Letter: 1
Question
16-bit incrementer, and 8-bit multiplier. You can use below entity declaration for your design. The least-significant 8 bits of A and B are used as inputs of the multiplier. The output will be 16 bits. The operation of arithmetic unit depends on the value of input Select.
entity ArithmeticUnit16bit is
Port(A : IN std_logic_vector(15 downto 0); -- Input
B : IN std_logic_vector(15 downto 0); -- Input
Op_Sel: IN std_logic_vector(1 downto 0);--operation selection
ArithOut: OUT std_logic_vector(15 downto 0); -- Result
Cout : OUT std_logic); --carry out bit of operation
end ArithmeticUnit16bit;
Note:
8-bit multiplier has only 16 bits as output, the carry out of arithmetic unit must be 0 when a multiplication operation is performed.
The carry out of this unit must be 1 after incremental operation is performed when current A’s value is 0xFFFF (Overflow case) For example: if A = 0xFFFF, then A = A + 1 = 0x0000 and carry out = 1
REPORT: VHDL CODE PLEASE
Explanation / Answer
entity ArithmeticUnit16bit is
Port(A : IN std_logic_vector(15 downto 0); -- Input
B : IN std_logic_vector(15 downto 0); -- Input
Op_Sel: IN std_logic_vector(1 downto 0);--operation selection
ArithOut: OUT std_logic_vector(15 downto 0); -- Result
Cout : OUT std_logic); --carry out bit of operation
end ArithmeticUnit16bit;
architecture Behavioral of ArithmeticUnit16bit is
signal tmp: std_logic_vector(16 downto 0):="00000000000000000";
begin
process (A,B,Op_Sel)
begin
case S is
when "00" =>tmp<=A(7 downto 0)*B(7 downto 0);
when "00" =>tmp<= A+B ;
when "01" =>tmp<=A-B;
when "11"=>tmp<=A+1;
end case;
cout<=tmp(16);
ArithOut<=tmp(15 downto 0)
end process;
end Behavioral;
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