Project: What can I do with this project? Explain the question please? Title: 3

Question

Project: What can I do with this project? Explain the question please?

Title: 3 bit serial in parallel out shift register with asynchronous active low reset

-Use Rasing edge D-FF with asynchronous active low reset

-D-FF should use 4 transmission Gate in its implementation

-Each D-FF should have only 3 input (D, Clk, Reset) and 2 output (Q, Q not)

-Implement in 120 nm

-Need to reasoning minimize area of D-FF and shift register

-Run DRC should have 0 DRC violations

-Do layout

-Simulate D-FF and S/R

-Using DSCH schematic editor to capture schematic and test

-can use Microwind to layout

The report will submit:

1.   Block diagram of R S/R and D ff

2.   Transistor schematic of S/R and D-FF

3.   Stimulation S/R and D fff

4.   Layout Dff and S/R

5.   DRC result on S/R and Dff

6.   Area calculation of D ff and S/R

Explanation / Answer

consult this: http://www.allaboutcircuits.com/textbook/digital/chpt-12/serial-in-parallel-out-shift-register/

https://en.wikipedia.org/wiki/Shift_register

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