Using verilog, Design a 16-bit register bank consisting 8 registers with two rea
ID: 1717061 • Letter: U
Question
Using verilog, Design a 16-bit register bank consisting 8 registers with two read ports and one write port. Read operation on each port gives 16 bit data. Write port needs 16 bit data and address (register number) to perform write operation. The write_enable signal has to remain high during write operation. Register 0 (R0) is always 0 and write operation is forbidden on R0. Reset would to make all the 7 registers to zero. Read or Write operation can be done only at the positive edge of clock cycle.If write and read operation are done on the same clock cycle, reading through port 1 will give the old values. Reading through port 2 will provide the new values. A set of hidden registers is available to hold intermediate values. Port 2 has access to those intermediate registers only when they are holding intermediate values. Then write a TestBench to perform the tasks and display results. Using Verilog!!!
Explanation / Answer
A)
1)The decoder has a single 3-Bit input and a 8-bit output. That exactly one of the output of a decorder is one; and will be zero.If the 3-bit input is n, then nth is bit set to one, As with the multiplexer will be a useful primitive for later
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