I need a completed VHDL code with concurrent signal assignment statements and a
ID: 1766129 • Letter: I
Question
I need a completed VHDL code with concurrent signal assignment statements and a block diagram. Thank you!!!
I know there are some solutions refer to this question on chegg, but those are really unclear,
so please read the question and help me to firgure out the answer, do not cheat!!!
4.6 We wish to design a shift-left circuit manually. The inputs include a, which is an 8-bit signal to be shifted, and ctrl, which is a 3-bit signal specifying the amount to be shifted. Both are with the std.logic.vector data type. The output y is an 8-bit signal with the std.logic.vector data type. Use concurrent signal assignment statements to derive the circuit and draw the conceptual diagram.Explanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity shift_left is
port(
din : in STD_LOGIC_VECTOR (7 downto 0);
ctrl : in STD_LOGIC_VECTOR (2 downto 0);
dout : out STD_LOGIC_VECTOR (7 downto 0)
);
end shift_left;
architecture behavioral of shift_left is
signal y0, y1, y2, y3, y4, y5, y6, y7 : STD_LOGIC_VECTOR (7 downto 0);
begin
-- evaluating signal for the left shift
-- yn represents the shift in input signal din by n times
y0 <= din(7 downto 0);
y1 <= din(6 downto 0) & '0';
y2 <= din(5 downto 0) & '0' & '0';
y3 <= din(4 downto 0) & '0' & '0' & '0';
y4 <= din(3 downto 0) & '0' & '0' & '0' & '0';
y5 <= din(2 downto 0) & '0' & '0' & '0' & '0' & '0';
y6 <= din(1 downto 0) & '0' & '0' & '0' & '0' & '0' & '0';
y7 <= din(0) & '0' & '0' & '0' & '0' & '0' & '0' & '0';
dout <= y0 when (ctrl = "000") else
y1 when (ctrl = "001") else
y2 when (ctrl = "010") else
y3 when (ctrl = "011") else
y4 when (ctrl = "100") else
y5 when (ctrl = "101") else
y6 when (ctrl = "110") else
y7;
end behavioral;
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