PLEASE WRITE THE TESTBENCH FOR THIS CODE!!! module fpadd(a,b,out,e1,e2,exy,s1,s2

Question

PLEASE WRITE THE TESTBENCH FOR THIS CODE!!!

module fpadd(a,b,out,e1,e2,exy,s1,s2,sr,sign,m1,m2,mx,my,mxy,mxy2);
input[31:0]a,b;

output reg [31:0]out;
output reg [7:0]e1,e2,exy;
output reg s1,s2,sr,sign;
output reg [23:0]m1,m2,mx,my;
output reg [24:0]mxy,mxy2;
reg [7:0] diff,i,x;
always @ (a or b)
begin
s1=a[31];
s2=b[31];
e1=a[30:23];
e2=b[30:23];
m1[23]=1'b1;
m2[23]=1'b1;
m1[22:0]=a[22:0];
m2[22:0]=b[22:0];

if(e1==e2)
begin
mx=m1;
my=m2;
exy=e1+1'b1;
sign=s1;
end
else if(e1>e2)
begin
diff=e1-e2;
mx=m1;
my=m2>>diff;
exy=e1+1'b1;
sign=s1;
end
else
begin
diff=e2-e1;

mx=m2;
my=m1>>diff;
exy=e2+1'b1;
sign=s2;
end

sr=s1^s2;
if(sr==0)
begin
mxy=mx+my;
sign=s1;
end
else
begin
mxy=mx-my;
end
mxy2=mxy;

if(s1==0 && s2==0)
sign=1'b0;
else if (s1==1 && s2==1)
sign=1'b1;
else if (s1==0 && s2==1)
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b1;
else
sign=1'b0;
end
else
begin
if(e1<e2 || ((e1==e2) && (m1<m2)))
sign=1'b0;
else
sign=1'b1;
end

for(i=0;i<24;i=i+1)

if (mxy[24]==0)
begin
mxy = mxy << 1;
exy = exy - 1;
end

if (mxy[23:0]==24'b0000000000000000000000000)
begin
out=32'b00000000000000000000000000000000;
end
else

begin
out= {sign,exy,mxy[23:1]};
end
end

endmodule

Explanation / Answer

module testfile(); // test bench declared

reg[31:0]a,b; // reg for input and wire for output

wire[31:0]out;
wire [7:0]e1,e2,exy;
wire s1,s2,sr,sign;
wire [23:0]m1,m2,mx,my;
wire [24:0]mxy,mxy2;

//module called

  module fpaddtest1(.a(a),.b(b),.out(out),.e1(e1),.e2(e2),.exy(exy),.s1(s1),.s2(s2),.sr(sr),.sign(sign),.m1(m1),.m2(m2),.mx(mx),.my(my),.mxy(mxy),.mxy2(mxy2));

// we add the test cases  

initial begin

    a = 32'h8d56db9e;

    b = 32'h21338a78;

    #100

    a = 32'hab317378;

    b = 32'h21320a78;

    #100

a = 32'habcda378;

    b = 32'h2132cda8;

    #100

a = 32'ha2917378;

    b = 32'h21328278;

    #100

a = 32'hab3bda78;

    b = 32'hbda20a78;

    #100

    $finish;

  end

endmodule

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