1. (a) Consider the Verilog code fragment below assign a10\'b 001_010_101.1; Is

Question

1. (a) Consider the Verilog code fragment below assign a10'b 001_010_101.1; Is this syntactically correct? If so, what is the decimal equivalent of the value of a after the above line executes? (b) Consider the bufif0 built-in gate which we discussed in class. Assume the input is A, the control signal is C and the output is W. Write a single line of dataflow Verilog which implements the same logic as the bufif0 gate (c) Consider the Verilog code fragment below assign p = 4,b 0011; assign q4'b 111; t {r , s); = Write down the values of r, s, t, u and v (d) Consider the Verilog code fragment below always begin (v or y) r = v; // line 1 s

Explanation / Answer

1. (a)

assign a = 10'b 001_010_10_1_1;  

The above statement is correct. When this statement is executed 'a' will be assigned to decimal value 171.

NOTE: underscores among the bits are used for better visibility.

1.(b)

The single line code for given description is given below. Note that C is the control signal, input is A and output is B.

// BUFIF0 generally represents a single output buffer gate with active-low control signal. It can be modelled as a nand gate. When control C is 1 the output will be z. and when it is 0, the output will be input signal.

assign W= C ? 1'bz : A;

1.(c)

// p = 4b' 0011;

//q= 4b' 11x1;

r = ^p; //reduction XOR => r= 0 xor 0 xor 1 xor 1 => r = 0

s = &q; //reduction AND => s=( 1 and 1 and x and 1 ) => s=x

t = {r,s}; // concatenation => t = 2b' 0x

u = |t; //reduction OR => u = (0 or x ) => u = x

v = &u //reduction AND => v = x

1. (d)

In commented line 2 of the given code, 't' is used before its assignment hence it will block the execution. So we have to interchange the lines in a way that, the interdependancy will be removed. The corrected code is given below.

always @ (v or y)

begin

r=v; // line 1

t = r; //line 3

s <= t; //line 2

u <= y; //line 4

end

}

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