Q3) Multiplexer A multiplexer is a device that selects one of several analog or

Question

Q3) Multiplexer A multiplexer is a device that selects one of several analog or digital input signals and forwards the selected input into a single line. A multiplexer of 2 inputs has n select lines, which are used to select which input line to send to the output. Please design the entity as well as the test bench for a 4-to- 1 multiplexer. For this multiplexer, please use the following to refer to the inputs/outputs of the circuit: 13, 12, , 10 as data inputs; S1 and SO as selection inputs; and out0 as data output Your entity design is Your test bench design is: In your test bench design, please enable each one of the4 inputs at one time. For example enable 10 to go through the multiplexer first by letting SI = ‘0, and S0 = .0. For this case, set 10 to be at "O" for 50ns, and then “1" for 50ns. After this, change S1, S0 values to let II (go through '0* and 'each for 50ns), 12 (go through '' and each for 50ns), and 13 (go through ‘0, and .1, each for 50ns) pass the multiplexer correspondingly The result waveforms are: Please select the signals to be simulated in the following order: S1, S0, 13, 12, , 10, Out0.

Explanation / Answer

The vhdl code for 4x1 mux is given below

-----------VHDL CODE FOR* MUX--------------

library ieee;
use ieee.std_logic_1164.all;
entity mulplex is
port( I0,I1,I2,I3 : in std_logic; --input signals
       S1,S0: in std_logic;       --//slection lines
       out0: out std_logic);      --//output signal
end mulplex;
architecture Behavioural of mulplex is
begin
process(I0,I1,I2,I3,S1,S0)is
begin
    if (S0 ='0' and S1 = '0')then
    out0 <= I0;
    elsif (S0 ='1' and S1 = '0') then
    out0 <= I1;
    elsif (S0 ='0' and S1 = '1') then
    out0 <= I2;
    else
    out0 <= I3;
    end if;
end process;
end Behavioural;

----------------TEST BENCH---------------------

library ieee;
use ieee.std_logic_1164.ALL;

entity test_mux is
end test_mux;

architecture behavior of test_mux is

    -- Component Declaration for the Unit Under Test (UUT)

component mulplex is
port( I0,I1,I2,I3 : in std_logic; --input signals
       S1,S0: in std_logic;       --//slection lines
       out0: out std_logic);      --//output signal
end component;
   signal S0 : std_logic := '0';
   signal S1 : std_logic := '0';
   signal I2 : std_logic := '0';
   signal I3 : std_logic := '0';
   signal I0 : std_logic := '0';
   signal I1 : std_logic := '0';
   --Outputs
   signal out0 : std_logic;
begin

    -- Instantiate the Unit Under Test (UUT)
   uut: mulplex PORT MAP (
          I0 => I0, I1 => I1, I2 => I2, I3 => I3, S0 => S0, S1 => S1, Z => Z );

   -- Stimulus process
   stim_proc: process
   begin
      -- hold reset state for 10 ns.
      wait for 10 ns;

    I0 <= '1';
    I1 <= '0';
    I2 <= '1';
    I3 <= '0';      

    S0 <= '0'; S1 <= '0';

      wait for 50 ns;

    S0 <= '1'; S1 <= '0';

      wait for 50 ns;

    S0 <= '0'; S1 <= '1';

        wait for 50 ns;  

    S0 <= '1'; S1 <= '1';

        wait for 50 ns;
      
    wait for 10 ns;
    I0 <= '0';
    I1 <= '1';
    I2 <= '0';
    I3 <= '1';      

    S0 <= '0'; S1 <= '0';

      wait for 50 ns;

    S0 <= '1'; S1 <= '0';

      wait for 50 ns;

    S0 <= '0'; S1 <= '1';

        wait for 50 ns;  

    S0 <= '1'; S1 <= '1';

        wait for 50 ns;
      
    end process;

end;

(if you have any query leave a comment, Thank you)

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