I m having problems with the testbench can u fix it for me its written at the en
ID: 1796686 • Letter: I
Question
I m having problems with the testbench can u fix it for me its written at the end.Use Verilog to design a module that performs one of four operations on two 4-bit inputs to produce one 4-bit output as specified below. Use always and case statements, and begin – end statements if needed. Include explanatory comments in the module’s Verilog code as needed. Use the text editor within ModelSim or any text editor that you like to write the Verilog code.
Inputs a[3:0], b[3:0], s[1:0]
Outputs y[3:0]
Function s function
0 y = a + b, unsigned add
1 y = a AND b, bit-wise AND
2 y = NOT a, bit-wise NOT of input a; ignore input b
3 y = 0, ignore inputs a and b
Write a Verilog testbench that:
a.uses Verilog loop statements to exhaustively test your module by applying all possible input combinations.
b.uses Verilog if-else and case statement to check that the module’s output is correct for the applied input pattern, and uses $display to print a pass/fail message to the console for each applied pattern.
decoder
module decoder (a, b, s, y);
input wire [3:0] a, b;
input wire [1:0] s;
output reg [3:0] y;
assign a = 4'b0000;
assign b = 4'b0000;
always @*
if (s == 2'b00)
y = a + b;
else if (s == 2'b01)
y = a & b;
else if (s == 2'b10)
y = ~a;
else
y = 0;
endmodule
testbench
`timescale 1 ns/10 ps
module decoder_testbench;
wire [3:0] a,b;
wire [1:0] s;
reg [3:0] y;
decoder utt (a, b, s, y);
initial begin
for (s = 0; s <= 3; s = s + 1)
begin
for (a = 0; a <= 15; y = a + 1)
for (b = 0; b <= 15; y = 1 + b)
y = a + b;
$display;
end
end
endmodule
Explanation / Answer
Inputs a[3:0], b[3:0], s[1:0]
Outputs y[3:0]
Function s function
0 y = a + b, unsigned add
1 y = a AND b, bit-wise AND
2 y = NOT a, bit-wise NOT of input a; ignore input b
3 y = 0, ignore inputs a and b
Write a Verilog testbench that:
a.uses Verilog loop statements to exhaustively test your module by applying all possible input combinations.
b.uses Verilog if-else and case statement to check that the module’s output is correct for the applied input pattern, and uses $display to print a pass/fail message to the console for each applied pattern.
decoder
module decoder (a, b, s, y);
input wire [3:0] a, b;
input wire [1:0] s;
output reg [3:0] y;
assign a = 4'b0000;
assign b = 4'b0000;
always @
if (s == 2'b00)
y = a + b;
else if (s == 2'b01)
y = a & b;
else if (s == 2'b10)
y = ~a;
else
y = 0;
endmodule
testbench
timescale 1 ns/10 ps;
module decoder_testbench;
wire [3:0] a,b;
wire [1:0] s;
reg [3:0] y;
decoder utt (a, b, s, y);
initial begin
for (s = 0, s <= 3, s = s + 1)
begin
for (a = 0, a <= 15, y = a + 1)
for (b = 0, b <= 15, y = b+1)
y = a + b;
$display;
end
end
endmodule
i hope it helps you dear :))
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