I need to design a 4-bit serial adder (VHDL code or schematic) which includes tw

Question

I need to design a 4-bit serial adder (VHDL code or schematic) which includes two shift registers and a single full-adder to perform the following functionality with proper timing controls. Two 4-bit inputs A and B will be set by eight switches on your Xilinx board. Inputs S will control two modes of operation, when S=0 your circuit will perform a serial addition of A and B,A+B,and when S=1 output will be subtraction of B from A,A-B When the 4-bit inputs A and B, and S switch is ready, pressing a pushbutton R will start operation and without further inputs the result will be ready and stable on one of the 7-segment displays. Changing the inputs A,B and S will not change the result on the 7-segment display until the pushbutton R is pressed again.

Explanation / Answer

the Full Adder is made up of two Half Adders and a -- OR Gate. We are going to build this VHDL Full Adder -- based on that same structure. -- -- 1] First we will design a Half Adder entity -- 2] Second we will desgin a OR gate entity. -- 3] Third we will combine those two entities to form -- a Full Adder. -- -- Note #1: -- -- To build the Half Adder using structural design -- techniques, we need a XOR Gate and a AND Gate. So -- in the first portion of the design we will define a -- XOR Gate and a AND Gate, and then use them to -- design the Half Adder. -- -- It is very important to learn structural design -- (RTL) strategies because as your assignments become -- larger and larger, knowledge of register transfer -- level (RTL) design strategies become indispensable. ------------------------------------------------------------- -- Here we define the AND gate that we need for -- the Half Adder library ieee; use ieee.std_logic_1164.all; entity andGate is port( A, B : in std_logic; F : out std_logic); end andGate; architecture func of andGate is begin F

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