read The description of the operation of the circuit is contained in the archite

Question

read The description of the operation of the circuit is contained in the architecture definition or body. The architecture body defines the interrelationship of the signals and the type of circuit used (sequential or combinatorial). The architecture body is separated from the design entity interface to allow for different implementations. The subprogram features of VHDL provide subroutines and functions to support many different ways to implement a desired function, each possessing a unique set of performance and cost trade-offs. The basic form of the architecture body is shown in Figure 1.3. Figure 1.3: Architecture Body Syntax ARCHITECTURE name OF entity-name IS SIGNAL signal-name : signal-type; SIGNAL signal-name : signal-type; BEGIN -- Process statement -- Concurrent Procedure Call -- Concurrent Signal Assignment -- Selected Signal Assignment -- Component Instantiation Statement -- Generate Statement END name; The architecture body consists of an architecture name and the name of a previously declared ENTITY file. Each ARCHITECTURE file must be directed related (or bound) to a corresponding ENTITY file. Internal signals and variables can be declared in the architecture body. These represent values that are not input or output, but are required for defining the circuit operation. A SIGNAL is a name given to an internal connection within an architecture description, and a VARIABLE is often used to simplify descriptions by storing intermediate results. Both of these will be further explained later. it lists "signal" and "variable". what their difference is? give examples

Explanation / Answer

There are three major difference between a signal and a variable in the VHDL Coverage wise – Signals has coverage to whole architecture, it can be access from any place in a Architecture of entity A variable is local to a procedure defined in the architecture Behavior wise – Signal assignments executes concurrently, It means, if we have 5 signals assignment, then it depends on the simulator to decide which signal to be assigned first In case of variable, it takes the value immediately OR in other language, it executes sequentially Synthesis Wise – If we have 2 variable and two signals used in a process, the variables infer just a wire during synthesis, but the signals infer a Flop.

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