Using normalized textbook Logical Effort values (e.g. a \"2 over 1\" unit invert

Question

Using normalized textbook Logical Effort values (e.g. a "2 over 1" unit inverter has a relative delay of 1, etc.), design a static CMOS circuit that implements an 11-input OR gate. Each input is driven by a unit inverter and the output drives 403 unloaded unit inverters. Optimize for minimum propagation delay of the total circuit, including all of the inverters. Consider using multiple stages of logic. Tabulate the circuits you examined Report the maximum delay. Show your calculations and final schematic, including relative transistor sizes.

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