I was wondering if anyone could develop a VHDL model for the MIPS processor. 1.

Question

I was wondering if anyone could develop a VHDL model for the MIPS processor.

1. Develop a VHDL model for the MIPS processor. The model should simulate a 4-stage (Fetch, Decode, Execute, and Write-back pipeline design.

2. The instruction memory should be modeled as a ROM, which can be part of the Fetch unit.

3. The data memory should be modeled as a read/write Random Access Memory, which can be included within the Write-back stage.

4. The register file should be modeled as a 3-port, 32 word, Random Access Memory, which can be included within the Decode unit.

5. It should be assumed that all RAW data hazards will be handled using data forwarding between the Execute state and the Decode stage.

6. Branch hazards should be resolved statically, i.e. assume that branch delay slots are filled either with a valid instruction or with nops.

7. Implement the following R format instructions: jr, add, sub, and, or, slt, lw, sw, sb

8. Implement the following I format instructions: beq, bne lbu, addi, subi

9. Implement the following J format instructions: jal, j and nop.

10. Submit the VHDL code for each pipe stage as a separate module.

11. Combine the pipe stages into a single hierarchical model and submit the VHDL code for the top-level model.

Thanks

Explanation / Answer

Traditionally, undergraduate computer architecture laboratory courses have used special purpose software simulators to aid in the design and modeling of a simple computer. This model of a simple computer is used to explain and reinforce many of the new ideas presented in lectures. In recent years, many such courses have been based on behavioral or RTL level simulations only. A methodology is described using VHDL based rapid prototyping for top down hierarchical design, synthesis, and a full gate level timing simulation of a 32-bit RISC processor through the use of advanced CAD tools. These commercial CAD tools are available to universities at substantial educational discounts. A VHDL synthesis based laboratory course was developed to accompany our undergraduate computer architecture course sequence. Computer and electrical engineering majors take this two-quarter course sequence. Our goal was to enable students to design and develop a realistic computer system simulation using many of the recent advances in CAD tools for logic synthesis and simulation. One of these recent developments, VHDL, Very High Speed Integrated Circuit Hardware Description Language, is now widely used to model and simulate digital circuits. VHDL has syntax similar to Pascal or ADA. VHDL Synthesis tools are available which automatically translate a high level VHDL behavioral model into a gate level digital logic schematic. Increasing the level of abstraction using such automatic synthesis tools produces substantial reductions in development time for complex digital circuits and is now widely used in industry. II. Computer Architecture Design Laboratory The required undergraduate computer architecture course sequence consists of two, four hour, one quarter courses, Computer Engineering 2510 and 3510. Computer and electrical engineering students at the Georgia Institute of Technology take these courses in sequence. The goals of this course sequence are to introduce students to assembly language programming, computer arithmetic, computer architecture and to provide an introduction to modern digital CAD tools. At the end of the sequence, students should have a basic understanding of computer operations from the high-level language programming level to the gate level implementation of the computer system. Students are already familiar with digital design, computer programming in a high level language, Field Programmable Gate Arrays, and VHDL based modeling and simulation of simple digital logic circuits from prerequisite courses. Computer Architecture I and II is taught every quarter and has an enrollment of around 400 students per year. Course lectures are held three hours a week and three hours of laboratory work per week are required. Several tools such as assemblers, compilers, and CAD tools were collected from a variety of sources for this laboratory and many are available free of charge to educational users via the Internet. Links to many of these tools are included in the reference section. The lecture and laboratory outline for Computer Architecture I and II is shown in Table 1. The MIPS 32-bit RISC assembly language, integer and floating point computer arithmetic, and several hardware implementations of the MIPS processor are contained in the course textbook [1]. In Computer Engineering 2510, Computer Architecture I, students complete three assembly language programming laboratory assignments using SPIM, a MIPS assembler and instruction level simulator. SPIM is a public domain program available free via anonymous ftp for UNIX, PC and MAC platforms [1,2,3]. The first two assembly language program assignments demonstrate integer operations, control structures, stack operations, and subroutine linkage. TABLE 1 Outline of Lecture and Laboratory Topics Week Computer Architecture I Laboratory Assignment Computer Architecture I Lecture Topic 1 SPIM tutorial MIPS RISC architecture 2 First assembly lang. Program MIPS instruction Set 3 " SPIM assembly language 4 Second assembly lang. Program Stacks and subroutines 5 MIPS C compiler Integer computer arithmetic 6 MIPS floating point program Floating point arithmetic 7 VHDL CAD tool tutorial Overview of VHDL 8 VHDL synthesis and simulation running a new test program MIPS processor hardware implementation and VHDL model 9 VHDL synthesis and simulation adding a new instruction Modifying hardware and VHDL to add new instructions and features 10 " Alternative microcoded MIPS Week Computer Architecture II Laboratory Assignment Computer Architecture II Lecture Topic 1 VHDL CAD tool tutorial Overview of pipelining 2 Pipelining the MIPS design Pipelining the MIPS hardware 3 " Pipeline control problems 4 Adding a hazard unit to the MIPS MIPS hazard detection hardware 5 " MIPS forwarding unit 6 Adding forwarding to the MIPS " 7 " MIPS branch flushing 8 Add branch flushing to the MIPS I/O devices and busses 9 " Caches and virtual memory 10 MIPS design on FPGA Introduction to parallel computers Students compare their hand written assembly code for the second assembly language program to the code generated by a C compiler that has compiled a program to perform the same operation. Lcc, a public domain retargetable C compiler, available free for UNIX workstations and PCs, is used for this step [4]. One of the target machines already supported by this compiler is the MIPS. MIPS assembly language source files generated by the compiler are then used by students to demonstrate compiler code generation. In the final assembly language program, students implement a floating-point function such as square root. The SPIM MIPS simulator supports floating-point instructions and operations. IEEE Standard 754 floating point format is used in the MIPS processor [1,2,3]. After the MIPS assembly language laboratory assignments, students have two laboratory assignments in which they modify a VHDL model of a MIPS RISC processor. A VHDL synthesis model of the MIPS was developed at Georgia Tech for use in this laboratory. VHDL source code for this model and instructions for several CAD tools are available using the link provided at the end of this paper. It should be noted that existing synthesis tools impose a number of restrictions upon the VHDL source code and require the use of a subset of standard VHDL. Most VHDL simulation models cannot be directly converted to a synthesis model since they use features not supported by the synthesis tools. VHDL has a Pascal or ADA based syntax and it includes several extensions which make it useful for modeling of digital circuits [5]. VHDL processes and modules execute in parallel. The WAIT statement suspends a process until the specified condition is true. A WAIT statement which waits for the clock signal to change is used to model and synthesize latches and flip-flops. Another VHDL extension is the AFTER keyword. The keyword, AFTER, followed by a time delay can be used to model the physical time delays present in digital circuits. These features permit VHDL to model the parallel operation of digital hardware even including physical time delays, if so desired. Behavioral VHDL based modeling of digital systems has been in use for several years. VHDL based logic synthesis is a newer development. In VHDL synthesis models, the time delays in the synthesized schematic are automatically simulated using special libraries for the target logic technology. An example of VHDL synthesis using the MIPS control unit is shown in Figs. 1 and 2. The VHDL source code is shown in Fig. 1 and the schematic automatically generated by the synthesis tool is shown in Fig. 2. The input to this module is the 6-bit instruction opcode, OP(5-0). The language support for standard logic vectors or arrays of bits, such as OP, greatly simplifies coding of the VHDL model. All busses and register values use the standard logic vector data type. It is possible to change the entire value of a vector with one assignment statement or to access smaller bit fields when needed. The outputs of this VHDL module are the various control signals used in the processor. The synthesis tool automatically performs logic minimization and multi-level logic synthesis. As an example, many of the intermediate level gate outputs are shared between the various output circuits shown in the schematic in Fig. 2. The original VHDL code had logic equations with six inputs for the opcode bits. More than two levels of gating are required for implementation, since the logic technology used for synthesis allows a maximum of four inputs per gate. -- control module (model of MIPS control module) library IEEE; use IEEE.std_logic_1164.all; entity control is port( signal Op : in std_logic_vector(5 downto 0); signal RegDst : out std_logic; signal ALUSrc : out std_logic; signal MemtoReg : out std_logic; signal RegWrite : out std_logic; signal MemRead : out std_logic; signal MemWrite : out std_logic; signal Branch : out std_logic; signal ALUop0 : out std_logic; signal ALUop1 : out std_logic); end control; architecture behavior of control is signal Rformat, Lw, Sw, Beq : std_logic; begin -- behavior of MIPS control Rformat

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