Write a Logic Diagram or schematic that will perform the following VHDL code. Li

Question

Write a Logic Diagram or schematic that will perform the following VHDL code.

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

entity stickycounter is

port(clk, reset, en : in std_logic;

       S : in std_logic_vector(7 down to 0);

       Done : out std_logic);

end stickycounter;

architecture stickycounter_arch of stickycounter is

signal count : std_logic;

begin

process(clk, reset, en, count)

begin

if (clk= %u20181%u2019 and en= %u20181%u2019)

if (reset= %u20181%u2019) then count <= S(0);

   else for i in 1 to 7 loop

   count <= S(i)

   end loop;

   end if;

end if;

if ( count = S(7) ) then Done <= %u20181%u2019;

elsif Done <= %u20180%u2019;

end if;

end stickycounter_arch;

Explanation / Answer

here the cide is not clear it have some symbols .

please clerfify the lines like (reset= %u20181%u2019) .

i am unable to understand %u20181%u2019 .

please re post the question with either the image of code or the clear code.

thanks

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