please, offer some explanation too; Consider the circuit shown in Fig. 1, with N

Question

please, offer some explanation too;

Consider the circuit shown in Fig. 1, with NMOS body terminal connected to the source terminal, and Vt0 = 0.4, lambda = 0, Kn = 4mA/V2. Analyze the circuit to determine the voltages at all the nodes and currents through all the branches. At what value of Vcc will the transistor be at the edge of the triode (linear) region? At what value of RD will the transistor be at the edge of the triode region? At what value of Rs will the transistor be at the else of the triode region?

Explanation / Answer

to find the the node voltage at Gate teminal

useing voltage division rule

Vg=1.2*Rg2/(Rg1+Rg2) = 1.2*100k/(100k+50k) = 0.8V

Id= 1/2 *k (Vgs-Vt)^2 =

or Id = (Vs-0)/R = Vs/10k

Vs/10k = 0.5*4m*(0.8-Vs-0.4)^2  

Vs/20 = Vs^2 -0.8Vs + 0.16

Vs^2-0.85Vs +0.16 = 0

solving

      Vs = 0.56 and 0.28

we shall take the value such that Vgs>Vt

          0.8-0.28 = 0.52 which is greater than Vt 0.4

so VS = 0.28

therefore Id = Vs/R = 0.28 /10 k = 0.028m A

Vd= Vdd - Id*Rd = 1.8 - 0.028*5k = 1.8 - 0.14 = 1.66V

b)now if we caliculate Vds = 1.66-0.8 = 0.86 V

                       Vds>Vgs-Vt

so the ckt is in saturation

for the ckt to be in triode Vds<Vgs-Vt

                               Vd<Vg-Vt

                              1.66<Vg-0.4

                               Vg>1.26V

c) Vd<Vg-Vt for the transistor to be in triode

    Vd < 0.8-0.4

Vd < 0.4

    Vd = Vdd - Id*Rd

   0.4 = 1.8 - 0.028m*Rd

solving

     Rd = 50K ohm

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