Using Quartus II, or an equivalent VHDL entry program, develop the text file and
ID: 1814873 • Letter: U
Question
Using Quartus II, or an equivalent VHDL entry program, develop the text file and simulation for the shift register specified specified below. Verify the timing diagram shown below. Attach the .vhd and simulation files.
I attached my code below but it does not work as I expected and not sure why it takes so long for my OUT to respond. PLEASE HELP?
Specs
For a 10-bit serial-in/serial-out shift register, determine Data out for the Data in and clock waveforms shown below. Assume that the register is initially cleared.
HERE IS MY CODE:
I am not sure why I am not getting the right response in my simulation. I get the response I want but not until close to the end of the time frame. With a dealy but not worried about that.
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY shift IS
PORT(
CLK,SI :IN STD_LOGIC;
SO :OUT STD_LOGIC);
END shift;
ARCHITECTURE circuit OF shift IS
signal sr_bit: std_logic_vector(9 downto 0):="0000000000";
BEGIN
PROCESS (CLK)
BEGIN
IF (CLK = '1')THEN
SO <= sr_bit(0);
sr_bit <= SI & sr_bit(9 DOWNTO 1);
END IF;
END PROCESS;
END circuit;
Explanation / Answer
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
Entity siso is
Port (si: in std_logic;
clk: in std_logic;
so:in out std_logic);
end siso;
architecture structural of siso is
component d_ff is
Port( d,clk: in std_logic;
q,qbar :in out std_logic);
end component;
Signal a1, a2, a3, d1, d2, d3, d4:std_logic;
begin
11:dff port map (si, clk, a1, d1);
12:dff port map (a1, clk, a2, d2);
13:dff port map (a2, clk, a3, d3);
14:dff port map (a3, clk, so, d4);
end structural;
library IEEE;
Use IEEE.STD_LOGIC_1164.All;
Use IEEE.STD_LOGIC_ARITH.All;
Use IEEE.STD_LOGIC_UNSIGNED.All;
entity dff is
Port (d : in std_logic;
clk : in std_logic;
q : in out std_logic;
qbar : in out std_logic);
end dff;
architecture Behavioral of dff is
begin
Process (d,clk)
Begin
if (clk
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