Consider the following Verilog statements: F1 = (x1 & x3) | (~x1 & ~x3) | (x2 &

Question

Consider the following Verilog statements:

F1 = (x1 & x3) | (~x1 & ~x3) | (x2 & x4) | (~x2 &~x4);

F2 = (x1 & x2 & ~x3 & ~x4) | (~x1 & ~x2 & x3& x4) | (x1 & ~x2 & ~x3 & x4) | (~x1 & x2 &x3 & ~x4);

a) Write complete Verilog code to implement F1 and F2
b) Use functional simulation to prove that F1 = ~F2

I'm very confused on this problem. Can someone please help me? Iwould greatly appreciate it! Will rate lifesaver for a thoroughdetailed solution to this problem

Explanation / Answer

The equation wants you to write the logic in verilog which isn'ttoo difficult at all. & means that you use an and circuitbetween the two, | means you use an or circuit and ~ means that itis a "not"(in other words, the inverse value) to write in verilog, simply declare your module and its components(x1,x2,x3,x4) then use "wires" to connect the components to eachother. It might be easier if you use assign to combine componentstogether (eg. y = ~x1 & ~x3). Syntax is key here so you'll haveto refer back to your verilog manual to help. for b, I'm guessing that to prove that F1= ~F2, you could make atruth table for all the inputs and outputs and show that theoutputs of F1 are the opposite of F2.

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