A CMOS circuit includes a pair of N-doped regions, separated by aP-doped channel

Question

A CMOS circuit includes a pair of N-doped regions, separated by aP-doped channel, as well as P-doped regions, separated by anN-doped channel. Although this forms PNP and NPN transistors,the bias of the regions is designed so the junctions are reversebiased and the electric field effects on the channel are supposedto control the MOS-FET transistors operations. There is afailure mode of a CMOS circuit where the bias conditions areviolated. What is the failure mode, what causes it, whateffects does it cause, and what is the simplest recovery mechanism.

Explanation / Answer

It causes hysteresis in the operating point.
When the substrate (body) is not biased properly with respect tothe body in both the NMOS and PMOS, there is a substrate currentand it forces the n-channel threshold voltage into the depletionmode (threshold voltage becomes negative) . To prevent thiscondition there should be sufficient substate bias.
This failure causes the n-channel threshold voltage into thedepletion mode. Thus the CMOS cannot work as aninverter.
A very high voltage supply can also cause the failure as then thecurrent will be very high. The source and substrate of both theNMOS and PMOS should be properly biased. This can be controlledwith proper doping. But the easiest recovery method is to increasethe substrate bias (Vsb) or decrease the supply voltage ifpossible.
I hope this helps you. The failure mode is similar to latch up conditions. It causes hysteresis in the operating point.
When the substrate (body) is not biased properly with respect tothe body in both the NMOS and PMOS, there is a substrate currentand it forces the n-channel threshold voltage into the depletionmode (threshold voltage becomes negative) . To prevent thiscondition there should be sufficient substate bias.
This failure causes the n-channel threshold voltage into thedepletion mode. Thus the CMOS cannot work as aninverter.
A very high voltage supply can also cause the failure as then thecurrent will be very high. The source and substrate of both theNMOS and PMOS should be properly biased. This can be controlledwith proper doping. But the easiest recovery method is to increasethe substrate bias (Vsb) or decrease the supply voltage ifpossible.
I hope this helps you.

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