write a VHDL module to implement a circuit that can generate a clock signal whos
ID: 1832023 • Letter: W
Question
write a VHDL module to implement a circuit that can generate a clock signal whose time period is a multiple of the input clock. A control signal F determines the multiplying factor. If F=0 the output signal has a time period twice that of the input clock. If F=1, the output signal has a time period twice that of the input clock. The portion of the clock cycle when the clock is 1 may be longer than the portion when it is 0, or vice versa. Use a counter with an active-high synchronous clear input.Explanation / Answer
entity Clock_Generator is
Port (Clk_in,F:in std_logic;
Clk_out:out std_logic);
end entity;
architecture arc_Clock_Generator of Clock_Generator is
signal count:integer range0 to 1;
signal count_clr:std_logic;
begin
clock_gen: process (Clk_in,F) is
begin
// F=1 clock signal will have the same period as the input clock
// and twice when F=0
if F='1' then
if Clk_in'event and Clk_in='1' then
Clk_out='1';
elsif Clk_in'event and Clk_in='0' then
Clk_out='0';
endif;
else
if Clk_in'event and Clk_in='1' then
if count=1 then
Clk_out='1';
count_clr='1' ;
count=0;
count_clr='0'
else
if count_clr='0' then
count=count+1
end if;
endif;
elsif Clk_in'event and Clk_in='0' then
if count=1 then
Clk_out='0';
count_clr='1' ;
count=0;
count_clr='0'
else
if count_clr='0' then
count=count+1
end if;
endif;
endif;
endif;
end process clock_gen;
end architecture;
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