The following code is taken from a VHDL file implementing a sequential circuit u
ID: 1840000 • Letter: T
Question
The following code is taken from a VHDL file implementing a sequential circuit using two processes (Second process is omitted). The sequential circuit has two inputs (X and clk) and one output (Z). ) Write down the state table implemented by the following VHDL code.
process(State,X) --Combinational Part
begin
case State is
when 0 =>
if X='0' then Z<='1'; Nextstate<=1;
else Z<='0'; Nextstate<=2; end if;
when 1 =>
if X='0' then Z<='1'; Nextstate<=3;
else Z<='0'; Nextstate<=4; end if;
when 2 =>
if X='0' then Z<='0'; Nextstate<=4;
else Z<='1'; Nextstate<=4; end if;
when 3 =>
if X='0' then Z<='0'; Nextstate<=5;
else Z<='1'; Nextstate<=5; end if;
when 4 =>
if X='0' then Z<='1'; Nextstate<=5;
else Z<='0'; Nextstate<=6; end if;
when 5 =>
if X='0' then Z<='0'; Nextstate<=0;
else Z<='1'; Nextstate<=0; end if;
when 6 =>
Z<='1'; Nextstate<=0;
end case;
end process;
Explanation / Answer
State table:
input Present state State representation Next state State representation Output x Q2 Q1 Q0 Z 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 0 1 1 3 1 0 0 1 0 2 1 0 0 4 0 0 0 1 1 3 1 0 1 5 0 0 1 0 0 4 1 0 1 5 1 0 1 0 1 5 0 0 0 0 0 0 1 1 0 6 0 0 0 0 1 1 0 0 0 0 0 1 0 2 0 1 0 0 1 1 1 0 0 4 0 1 0 1 0 2 1 0 0 4 1 1 0 1 1 3 1 0 1 5 1 1 1 0 0 4 1 1 0 6 0 1 1 0 1 5 0 0 0 0 1 1 1 1 0 6 0 0 0 0 1Related Questions
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