Note: . Use std_logic[_vector] and unsigned types. Write the VHDL architecture f
ID: 1841180 • Letter: N
Question
Note: . Use std_logic[_vector] and unsigned types.
Write the VHDL architecture for the entity:
entity controller is
port ( en, f, clk : in std_logic ;
G, Y : out std_logic ) ;
end controller ;
that implements a state machine with the following state transition diagram:
where the output G is 1 in states A and B and 0 otherwise and the output Y is 1 in state B and 0 otherwise. The transition condition a is that en is 1. The transition condition b is that f and en are both 1. The state remains the same for all other input conditions. State transitions happen on the rising edge of clk.
b (BExplanation / Answer
find the VHDL code as given below:
as given we have two outputs G and Y
G is one when present state is A or B otherwise it is 0.
Y is one when present state is B other wise it is 0.
so as otput depends on present state only it is moore machine.
library ieee;
use ieee.std_logic_1164.all;
entity controller is
port (
clk : in std_logic;
rst : in std_logic;
en : in std_logic;
f : in std_logic;
G : out std_logic;
Y : out std_logic);
end controller;
architecture rtl of controller is
type state_type is (A, B,C);
signal state : state_type;
begin
process (clk)
begin
if(rising_edge(clk)) then
if (rst = '1') then
state <= A;
elsif(rst = '0') then
case (state) is
when A =>
G <= '1';
Y <= '0';
if (en = '1') then
state <= B;
else
state <= A;
end if;
when B =>
G <= '1';
Y <= '1';
if ((en = '1') and (f = '0')) then
state <= C;
elsif((en = '1') and (f = '1')) then
state <= A;
else
state <= B;
end if;
when C =>
G <= '0';
Y <= '0';
if (en = '1') then
state <= A;
else
state <= C;
end if;
end case;
end if;
end if;
end process;
end rtl;
as given in the problem statement if we have other input conditions than state remain the same so,
when state is A and en = 0
state <= A;
when state is B and if en is not equal to 1
state <= B;
when state is C and en = 0
state <= C;
i am using else statement for all thie three condition.
code is working properly.
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