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Need help keep coming up with error below when trying to compile library ieee; u

ID: 1846241 • Letter: N

Question

Need help keep coming up with error below when trying to compile

library ieee;

use ieee.std_logic_1164.all;

ENTITY ushift4 IS

PORT (clk, clrb, sl_in, sr_in : in bit;

mode : in bit_vector ( 1 downto 0 );

d : in bit_vector ( 3 downto 0 );

q : inout bit_vector (3 downto 0 ));

END ushift4;

ARCHITECTURE behav OF ushift4 IS

BEGIN

PROCESS (clk, clrb)

begin

-- Asynchronous, active-low Clear input:

if clrb = '0' then q <= "0000" ;

-- Rising edge-triggered D flip-flops:

elsif clk'event and clk = '1' then

case mode is

-- "Do Nothing" mode: retain current flip-flop outputs

when "00" => null;

-- Shift Right Serial Input mode:

when "01" =>

q <= (q srl 1) or (sr_in & "000") ;

-- Shift Left Serial Input mode:

when "10" =>

q <= (q sll 1) or ("000" & sl_in) ;

-- Parallel (Broadside) Load mode:

when "11" => q <= d ;

end case;

end if;

end process;

Explanation / Answer

Please end the architecture body. add one last line "end behav;" and then your program will be fault free.

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