Could someone please write a verilog code for the following problem. I did ask t

Question

 Could someone please write a verilog code for the following problem. I did ask this question before but they forgot to include the 1Hz in the code. Please write the complete code with test bench code.   

 Use hierarchical design method to implement design below and download it on FPGA. Implement 4-stage right rotation registers which are rising-edge triggered by 1Hz clock. The rotation registers have several control signals: a). asynchronous high-active reset signal b). asynchronous high-active load signal which allows to load parallel data p[0], p[1], p[2], and p[3]. 

Explanation / Answer

http://www.chegg.com/homework-help/questions-and-answers/use-hierarchical-design-method-implement-design-download-fpga-implement-4-stage-right-rota-q5024768

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