%3Cp%20class%3D%22MsoNormal%22%3EPlease%20give%20me%20complete%20explanation%20w

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%3Cp%20class%3D%22MsoNormal%22%3EPlease%20give%20me%20complete%20explanation%20why%20it%0Atakes%207%20clock%20cycles%2C%20I%20need%20%3Cspan%20class%3D%0A%22c1%22%3Eexplanation%20%3C%2Fspan%3Eonly%20for%20part%20b%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%26nbsp%3B%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3EQuestion%3A%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%0Ahttps%3A%2F%2Fwww.dropbox.com%2Fs%2F2sf0a67yf099ivz%2FImage.jpg%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%26nbsp%3B%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%3Cbr%20%2F%3E%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%3Cbr%20%2F%3E%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3EAdditional%20documents%20that%20you%20might%20need%3A%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%3Cbr%20%2F%3E%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%0Ahttps%3A%2F%2Fwww.dropbox.com%2Fs%2F8iqi8vagn9ruw27%2FChapter5-Handout-.pdf%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%3Cbr%20%2F%3E%3C%2Fp%3E%0A%3Cp%20class%3D%22MsoNormal%22%3E%0Ahttps%3A%2F%2Fwww.dropbox.com%2Fs%2Fn5s5r8x76eeem1v%2Fcomputer%2520system%2520architecture.compressed_Compressed.pdf%3C%2Fp%3E%0A

Explanation / Answer

T0 AR <-- PC
During T0, the address (006) is loaded into AR.

T1 IR <--M[AR]
During T1, the instruction code is loaded into IR and PC is incremented

T2   AR <-- 014, I <--0 D6 <--1
In T2, the address portion of this instruction, 014, is loaded into AR.
opcode was [0 110] indirect bit =0 . 110 is ISZ which makes D6 =1.

T3 is wasted since it is direct addressing

T4 DR <-- M[AR]
load contents of AR=014 in DR Now DR=-1

T5 DR=DR+1
DR= -1+1=0

T6 M[AR]<--DR since DR=0 PC=PC+1

Hence 7 cycles

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