Problem 1. (15 points) How to decide the shortest possible clock period for a sy

Question

Problem 1. (15 points) How to decide the shortest possible clock period for a synchronous
circuit with the flop-based clocking? What is the hold time of a register? How does the hold time
constrain the circuit delays for a synchronous circuit?

Explanation / Answer

Part A: As with my answer for part B, we can decide the minimum clock period for a circuit by using the equation: Tclk(min) >= Tcq(max) + Tcomb(max) + Tsetup You can think about it this way: the circuit can only be clocked as fast as a signal can propagate through the combinational logic and flip flop interior to its output, with a little time to spare (Tsetup) before the clock edge samples the signal. It's like making sure a runner can get in the door a little bit before you slam it shut. The hold time for a digital circuit is defined as the minimum amount of time that the input signal must remain stable (constant) after the clock edge comes. The hold time ensures that the correct value of the input gets sampled by the flipflop, because things like clock jitter could change exactly when it is sampled. The equation for the hold time constraint is as follows: Thold

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