Select the best answer from the alternatives for each question. Fill the ten bes

Question

Select the best answer from the alternatives for each question. Fill the ten best answers in the table below. The VHDL signals can be declared only: in the entity. before the architecture. between the architecture and the begin of the architecture. between the process and the begin of the process. The VHDL variables can be declared only: in the entity. before the architecture. between the architecture and the begin of the architecture. between the process and the begin of the process. The instantiation (port map) of a component: can be done anywhere in the architecture body. should be done at the start of the architecture body. can only be done between the architecture and the begin of the architecture. should be done at the end of the architecture body. The symbol used for signal assignment is::= = =

Explanation / Answer

ii) Can only be declared between the architechture and begin of the architecture.

iv) <=

vii) A slice contains only LUT's and Flipflops

viii) Four gates

X) Create only ROM

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