Exercise 2.2: Metastability and synchronizers A popular synchronizer was present
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Exercise 2.2: Metastability and synchronizers A popular synchronizer was presented in figure 2.6b and repeated in figure 2.18 alon with an illustrative timing diagram a) What do the gray areas in figure 2.18b represent? b) Which time parameters define the aperture windows width? c) Is it desirable that the aperture window be as narrow as possible or as wide as possible? d) Why must d remain stable during that time interva VWhat is metastabilit e) Why can synchronizers reduce the effect of metastability? f) Given the asynchronous input d shown in the figure, draw the waveforms for and itymu. (The initial part of go was already drawn; the delay included between t he clock edge and the signal edge is gam.) g) At which positive clock edge (first, second, etc) after d goes up does the signal actually delivered to the ISM (d go up h) Two short pulses (lasting less than one clock period) are included in the d wave form. Are they always detected? Explain Figure 2.6 SYNCHRONIZER APPLICATION cik f clk. tsetup thod data ready- do go clk. (a) Metastability (b) (c) Use of synchronizers 2.18 b) sync. Exercise 2.4: Fast Synchronized One-Shot Circuit #I Figure 2.20a shows the same arrangement of figure 2.10, implementing a fast one- shot circuit with asynchronous, and possibly short, input. This circuit is capable of detecting input pulses shorter (and also longer, of course the clock period, producin at the nan. oul put a pulse whose duration is always one clock period. Figure 2.20b shows the main signals involved in this circuit, with the plots for the clock and for the input (r) already completed some helping arrows are also included in the figure) a) Draw the waveforms for the internal (i1 to 4) and output y) signals. Donot forget to leave a little delay between a signal transition and the corresponding response b) What are the minimum and maximum durations of (in clock periods)? Why is the initial (edge detector) DFF also called a stretcherExplanation / Answer
1. Gray areas indicates the counts accumalated in DCAs with synchroniser.
2. For a synchroniser aperture window width is represnted by Tw.
3. It should be as narrow as possible but there are some efficiency contraints, due to which the aperture width has to kept in certain limits.
4. Very close agreement with from the previous calculations. T0 is different because of the extra delay through the slave latch and output buffers. This measured is from the master latch only. CLK was held high so the slave latch was transparent. By taking CLK low at just the right time we should be able to induce metastability in the slave and measure its also. Also note that for the overall flop is sensitive to the duty cycle of the clock
5. Whenever there are setup and hold time violations in any flip-flop, it enters a state where its output is unpredictable: this state is known as metastable state (quasi stable state); at the end of metastable state, the flip-flop settles down to either '1' or '0'. This whole process is known as metastability. In the figure below Tsu is the setup time and Th is the hold time. Whenever the input signal D does not meet the Tsu and Th of the given D flip-flop, metastability occurs. A very short hold time on the data input causes the master latch to enter its metastable state. Immediately after CLK rises the internal nodes A and B are fluctuating and have not yet reached a stable level. Eventually they have almost the same voltage as the latch enters the metastable state. The small V between A and B is then exponentially amplified by the gain of the crosscoupled gates, and finally the latch enters a stable state with Q driven high.
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