EXERCISE 2: Ring Counter In a normal shift register the bits shifted out are not
ID: 2072562 • Letter: E
Question
EXERCISE 2: Ring Counter In a normal shift register the bits shifted out are not saved. A Ring Counter is one variant of the shift register that preserves the data bits by rotating the shifted out bit back into the data input. 1. Rewire your SIPO shift register into a ring counter as follows: Disconnect the DATA constant, and connect Serial In to the Qd output. Switch the two wires going to the PR a CL inputs of flip-flop A only. 2. Initialize your ring counter by generating a temporary low pulse on NOT CLEAR, then return it to High. What is the initial 4-bit output pattern? 3. List below the resulting sequence of 4-bit output patterns (ie, 0000 as you Cycle the CLOCK 6 times, Does the output sequence repeat? If so, how many clock cycles are required to repeat? In general, how many unique output states would an TNT stage ring counter generate? EXERCISE 4: 4-bit Shift Register IC 74195N 1. This exercise looks at a medium scale IC that implements a 4-bit SIPO Shift Register all in one IC. Wire a 74195N 4-bit Shift Register IC as shown in the following diagram. Place Interactive Digital Inputs for all inputs, and Digital Probes as the output LEDs. QA QB QC QD U1 A B C D DATA SHIFT NOT LOAD 1 NOT CLEAR 1 CLA CLOCK 74195NExplanation / Answer
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