By filling in the five shaded portions, complete the following vhdl file, which

Question

By filling in the five shaded portions, complete the following vhdl file, which implements a binary up/down counter: -Up/Drown counter (ud = 0, count down; ud = 1, count up, clrn is asynchronous clear) LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY ud3 IS PORT (clrn, ce, clk, ud: IN STD_LOGIC; cout: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END; ARCHITECTURE Behavior OF ud3 IS SIGNAL q: STD_LOGIC_VECTOR (2 DOWNTO 0); -- the state of the machine BEGIN PROCESS(, clm) --any signal changing in sensitivity list starts process BEGIN IF clrn = '0' THEN -- active low asynch. clear q

Explanation / Answer

1.ENTITY ud3

2.ce,clk,ud

3.q=0

4.clk='1'

5.q+1

This is all required changes needed to above

Program.

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