Using a Verilog simulator, build a behavioral code and a testbench code for a ci
ID: 2073139 • Letter: U
Question
Using a Verilog simulator, build a behavioral code and a testbench code for a circuit that takes two 4-bit unsigned binary numbers A = A_3A_2A_1A_0 and B = B_1B_2B_1B_0 and a 2-bit user selection input S = S_1 S_0- The circuit should produce a 5-bit output O = O_4O_3O_2O_1O_0 according to the following table: Simulate the circuit for the 4-bit binary equivalent of each of the following eight test cases with 10 time units of separation between one test case and the next test case: A = 14, B = 5, S1S_0 = 00 A = 14, B = 5, S_1S_0 = 01 A = 14, B = 5, S_1S_0 = 10 A = 14, B = 5, S_1S_0 = 11 A = 5, B = 14, S_1S_0 = 00 A = 5, B = 14, S_1S_0 = 01 A = 5, B = 14, S_1S_0 = 10 A = 5, B = 14, S_1S_0 = 11 Save your behavioral code and testbench code and an image of the timing diagram results as a Word document and name the file "Veri1og02 yourStudeiitID.doc"Explanation / Answer
MODULE
module mod1 (a,b,s,o);
input [3:0] a,b;
input [1:0] s;
output reg[4:0] o;
always @(a,b,s)
begin
if (s = 2'b00)
o = (a>b)?a:b;
else if (s = 2'b01)
o = (a<b)?a:b;
else if (s = 2'10)
o = 2*a;
else
o = abs(a-b);
end
endmodule
TESTBENCH
module tb;
reg [3:0] ra,rb;
reg [1:0] rs;
wire [4:0] wo;
mod1 m1 (.a(ra),.b(rb),.o(wo));
initial
begin
ra = 4'd14;
rb = 4'd5;
rs = 2'b00;
#1
ra = 4'd14;
rb = 4'd5;
rs = 2'b01;
#1
ra = 4'd14;
rb = 4'd5;
rs = 2'b10;
#1
ra = 4'd14;
rb = 4'd5;
rs = 2'b11;
#1
ra = 4'd5;
rb = 4'd14;
rs = 2'b00;
#1
ra = 4'd5;
rb = 4'd14;
rs = 2'b01;
#1
ra = 4'd5;
rb = 4'd14;
rs = 2'b10;
#1
ra = 4'd5;
rb = 4'd14;
rs = 2'b11;
end
endmodule
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