Design a VHDL module for each of the following circuits. Your solutions should i

Question

Design a VHDL module for each of the following circuits. Your solutions should include VHDL source code with comments Assume positive edge trigger for all flip-flops. Use a text editor that will replace tabs with spaces for all your VHDL code Sixteen Bit Up/Down Counter Inputs: clock, reset, ud Outputs: 16-bit counter value Implement all 16-bits in a single VHDL process. The reset signal should synchronously reset the counter to zero. When ud = '1', the counter should increment on each clock cycle. When ud = '0', the counter should decrement on each clock cycle.

Explanation / Answer

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

  port(Clk, reset, ud : in std_logic;

        Q : out std_logic_vector(15 downto 0));

end counter;

architecture archi of counter is

  signal tmp: std_logic_vector(15 downto 0);

  begin

    process (Clk, reset)

      begin

        if (reset='1') then

          tmp <= "0000000000000000";

        elsif (Clk'event and Clk='1') then

          if (ud ='1') then

            tmp <= tmp + 1;

          else

            tmp <= tmp - 1;

          end if;

        end if;

    end process;

    Q <= tmp;

end archi;

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