Write the structural (i.e. using gate primitives, see Section 4.2) Verilog code
ID: 2079398 • Letter: W
Question
Write the structural (i.e. using gate primitives, see Section 4.2) Verilog code for a full adder with the module interface as shown in Figure 5-2. module fullAdder (input wire xi, input wire yi, input wire ci, output wire so, output wire co); Write the structural Verilog code for a four-bit adder with the module interface as shown in Figure 5-3 which uses four of the full adders from 5.2.1. Simulate in ModelSim to verify operation. module fourBitAdder (input wire [3:0] a, input wire [3:0] b, output wire [4:0] result);Explanation / Answer
module fulladder4bit(sum,c_out,a,b,cin);
input [3:0]a,b;
input cin;
output[3:0]sum;
output c_out;
wire c1,c2,c3;
full_adder fa1(sum[0],c1,a[0],b[0],cin);
full_adder fa2(sum[1],c2,a[1],b[1],c1);
full_adder fa3(sum[2],c3,a[2],b[2],c2);
full_adder fa4(sum[3],c_out,a[3],b[3],c3);
endmodule
module full_adder(sum1,c_out1,a1,b1,cin1);
input a1,b1,cin1;
output sum1,c_out1;
wire s11,c11,c21;
xor(s11,a1,b1);
and(c11,a1,b1);
xor(sum1,s11,c_in1);
and(s21,s11,c_in1);
xor(c_out1,s21,c11);
endmodule
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