Design a synchronous counter with output Z=1 of the last three bits in each of t

Question

Design a synchronous counter with output Z=1 of the last three bits in each of the input bit streams given Xa=101 Xb=010 Xa=010 Xb=110 input bit streams xa = 1011001 xb= 0101110 and the binary sum of the last three bits in each of the inputs bits streams i.e : Xa+Xb is 1 1 1. When the output Z is zero, no detection, the counter display should be indicating the number of previous detections up to 3 (if zero (00) it means that there were no previous detections). In addition, The counter circuit should count from 01 to 11 using binary numbers represented by two leds. The 4th detection will reset to 01 in order to count the next three detections. Try to minimize the number of parts used.The detection must be with overlap.

Explanation / Answer

The distinguishing feature of a synchronous digital system is that the circuit only changes in response to a system clock. For example, consider the edge triggered flip-flop which we discussed earlier in the course. Its key property is that the output changes to the input value only on receit of a clock pulse. Depending on how we design the flip flop, the change may occur on either the rising clock edge or the falling clock edge. In a big circuit, there may be other clock signals as well but all will have to be synchronized to the system clock and any other clock signal must have a known relationship in time to the system clock. A sequential circuit is one that goes through a sequence of states. For example, we could use a sequential circuit to control a traffic light system, or a washing machine programmer. There are many examples of sequential circuits in the real world, and the most complext of them is the central processing unit of a digital computer. Our focus in this lecture and the next, is the design of synchronous sequential digital circuits.

All flip-flops are connected to the same clock, and therefore all change at the same time. The ”state” of the system is defined as the Q outputs of the flip flops, and is stable between the clock pulses. The state is therefore a binary number of the form Q1Q2Q3..Qn. If there are n flip-flops then there are exactly 2 n possible states of the system. The state sequencing logic and output logic blocks are combinational circuits and their outputs are strictly functions of the inputs. Like all combinational logic circuits they suffer from transport delays, and may have spikes on the output in response to changing inputs. The behaviour of the system is defined by the transition of one state to another which occurs when a clock pulse is applied. As shown above, the output signals at any time depend only on the state of the system (defined by the flip-flop outputs). The next state depends on both the state and the input. We can indicate these in the functional forms.

A three-bit binary counter has one control input, C. When C = 0 the counter counts up even numbers, i.e. 0 2 4 6 0 etc, or in binary: 000 010 100 110 000 etc. When C = 1 the counter counts down odd numbers: 0 7 5 3 1 0 7 etc, or in binary: 000 111 101 011 001 000 111 etc. The counter may start in an undefined state (say, C = 1 and the counter output is 2 = 010). The sequence it goes through at start up is not important, but it must reach the 000 state from any starting state.

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