Below is a code for a signed adder, whose ports are all of type STD_LOGIC_VECTOR

Question

Below is a code for a signed adder, whose ports are all of type STD_LOGIC_VECTOR (industry standard). Analyze it and answer the questions below. (Suggestion: see example 3.9.)

a) This code uses the packages std_logic_1164 (line 3) and std_logic_arith (line 4). Are both necessary? Why?

b) Would the package numeric_std be useful here? Under which conditions could it be used?

c) There are type conversions in some lines of the code below. Which lines are they? What kinds of conversions are they (automatic, type casting, or with a type-conversion function)?

d) Do you expect any problems in the type conversion of line 16? Why?

e) Present a solution to remedy the problem in (d) by including additional computing steps in the code.

f ) Present another solution for the problem in (d), this time by replacing one of the de- clared packages.

g) Present one more solution for that problem, now using a ‘‘qualified’’ expression. h) Finally, in your opinion, what is the recommended code for such a signed adder?

Explanation / Answer

A. The IEEE 1164 standard defines a package design unit that contains declarations that support a uniform representation of a logic value in a VHDL hardware description and it is necessary. IEEE arith contains all logical and other operators which we use for addition, sub. or comparision etc. But it is not necessary.

B. numeric_std is standered library approved by IEEE. So, it is recommanded to use this package instead of std_arith package.

C. Input types are converted to wire to perform addition task @ line 14 and 15.(Type casting)

D. a_sig and b_sig are wire not registers so they can not store values.

E. REPLACE 14,15,16 LINES WITH SINGAL LINE sum <= a + b;

F. Replace std_arith packege by

G.

H. By using qualified we can directly use gates so it will exwcute fast and if we use some standred library instead of it than it will necessary import other packages.

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