I want to do transient anyalys for Pseudo-PMOS in cadence, but which does not wo

Question

I want to do transient anyalys for Pseudo-PMOS in cadence, but which does not work.

How to solve that?

4/ VerilogA for organic-vcos, org vgsexp, veriloga. include "constants vams include disciplines. vams module org vgsexpCvg vs, vd, outvgs, outgnd); input Vg VS vd output outvgs, outgnd electrical vg VS vd electrical outvgs outgnd parameter real m 0. 365 from CO: inf); parameter real K 7.85 pow 10 6 from CO inf) parameter real vthdrift -0.1 from K-1 inf inf) parameter real Wkd 2. 2 powC 10,-3) from CO: inf). parameter real 1 kd 20 pow 6) from (0: inf) real vgst, vds, ids, vdint, vsint, Cox, Eo, Epoly, kBOLTZ,T, Tc, const, REVERSE anal og begin Eo 8, 85 pow 10 2 Cox 66 pow 4) Epoly k BOLTZ 1. 38 pow 10, 23) 300 (m+ 1 if CVCvd) V(vs)) begin vdint vsint REVERSE end else begin dint VCVd) REVERSE 11 end vds (vdint vsint) -1 vgst (VCvg)- vsint vthdrift) -1; if CCvgst) 0) Const else if Cvgst vds) const (pow vgst, C2 m +2)))/ 2*m +2 else ids end if (REVERSE 1) begin VCoutvgs) ids end else begin VCoutgnd) ids end end

Explanation / Answer

The procedure followed by you is write except few errors.

First create output pin for output terminal of circuit,make sure that you should have all the input,output pins.

Make sure your power ports are proper.you can place the required instances from ploglib by entering I in the schematic window.No need of symbol view if it is there make sure it is right.

After the design is completed,select transient analysis with time(1/f) and moderate analysis.

input should be AC signal otherwise we dont get required output.Once check your circuit.

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