Please code this in verilog. Any input transition not explicitly referenced in t
ID: 2080984 • Letter: P
Question
Please code this in verilog.
Any input transition not explicitly referenced in the diagram keeps the machine in the same state. Moreover, if two or more switches are asserted simultaneously, no transition should occur. In other words, the switches are to be treated as one-hot and your design should enforce this provision. The only exception to this is SW0 which acts as the reset and should reset the FSM to S_00 regardless of all other switches or the pushbutton. (note you could use KEY1 pushbutton instead but it isn't clear that would be better).Explanation / Answer
ANSWER:
module FSM (input SW0, input SW1, input SW2, input SW3, input SW4, input clock);
reg [2:0] pstate, nstate;
wire [4:0] inp;
//This logic represents the flip flops of the FSM
always @ (posedge clock or posedge SW0) begin
if (SW0==1'b1) pstate <= 3'b0;
else pstate <= nstate;
end
assign inp = {SW4, SW3, SW2, SW1, SW0};
//Combinational logic of FSM
always @ (*) begin
case (pstate)
3'h0 : if (inp==(1'b1<<1)) nstate = 3'h1; else nstate = pstate;
3'h1 : if (inp==(1'b1<<1)) nstate = 3'h2; else if (inp==(1'b1<<3)) nstate = 3'h3; else nstate = pstate;
3'h2 : if (inp==(1'b1<<1)) nstate = 3'h4; else nstate = pstate;
3'h3 : if (inp==(1'b1<<3)) nstate = 3'h2; else if (inp==(1'b1<<2)) nstate = 3'h4; else nstate = pstate;
3'h4 : if (inp==(1'b1<<2)) nstate = 3'h2; else if (inp==(1'b1<<4)) nstate = 3'h0; else nstate = pstate;
endcase
end
endmodule
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