3. A MSP430 board has LED1 connected to P6.0, LED2 connected to P6.1, LED3 conne

Question

3. A MSP430 board has LED1 connected to P6.0, LED2 connected to P6.1, LED3 connected to P6.2, switch S1 connected to P2.0, and switch S2 connected to P2.1. The ACLK clock source is 32768 Hz. For the following program, answer questions (1) and (2). (1) (21 pts) Complete the program based on the comments.

#include int main(void) {

_________________________ // Stop watchdog timer

_________________________ // set P6.0, P6.1 and P6.2 to output direction

_________________________ // set LED1 and LED 3 on, LED2 off (active high)

_________________________ // use timer A0, select clock source ACLK; upmode; clear TAR

_________________________ // set TA0CCR0 so the timer can generate an interrupt request every 0.25 second

_________________________ // enables the interrupt request of the corresponding CCIFG flag. __enable_interrupt(); } // Timer A0 interrupt service routine

#pragma vector =TIMER0_A0_VECTOR __interrupt

void TIMER0_A0_ISR(void) {

_________________________ // toggle LED1, LED2, and LED3

}

(2) (4 pts) Describe what this program does overall.

Explanation / Answer

void Init_CLK(void)
{

//Pins:

P1SEL |= BIT0; // P1.0 from module (ACLK) - no LED
P1DIR |= BIT0; // P1.0 output
P2SEL |= BIT2; // P2.2 from module (SMCLK)
P2DIR |= BIT2; // P2.2 output
P7SEL |= BIT7; // P7.7 from module (MCLK)
P7DIR |= BIT7; // P7.7 output

// External Clock Sources:

   // LF XT1:
P5SEL |= BIT4+BIT5; // Port select XT1 (P5SEL.5 don't care)

// HF XT2
P5SEL |= BIT2+BIT3; // Port select XT2 (P5SEL.3 don't care)
UCSCTL6 &= ~XT2OFF; // Set XT2 On
UCSCTL6 |= XCAP_2; // Internal load cap (8.5pF). I am using no external capacitors at the moment.
// (Supposed configuration for used Quartz: 8.7pF)

   // Startup of quartz as XT1:
// XT1 is by default on as it is used default reference for the FLL - internal load caps?
// Loop until XT1,XT2 & DCO stabilizes
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag

UCSCTL6 &= ~XT2DRIVE0; // Decrease XT2 Drive according to
// expected frequency
UCSCTL4 |= SELA_5 + SELM_3 + SELS_4; // Select sources SACLK=XT2 and MCLK=DCO
// SMCLK source = default = DCOCLKDIV
UCSCTL5 |= DIVA_0 + DIVS_5 + DIVM_0; // SMCLK = DCOCLKDIV / 32

// FLL
UCSCTL3 |= SELREF_0; // Set DCO FLL reference = XT1 (default)

__bis_SR_register(SCG0);    // Disable the FLL control loop
UCSCTL0 = 0x0000;       // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5;       // Select DCO range 24MHz operation
UCSCTL2 = FLLD_4; // Set DCO Multiplier for 16,777,216Hz
// D*(N + 1) * FLLRef = Fdco
// 16*(31 + 1) * 32768 = 16,7MHz
// Settings: N = n = defaults, D = 1
// (Defaults: n=1, D=2, N=31)
__bic_SR_register(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);
}

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