Design a universal shift register. The shift register should be capable of the f

Question

Design a universal shift register. The shift register should be capable of the following operations (this will also reinforce the difference in logical and arithmetic shifting in arithmetic right shifting you need to copy the sign bit ellipsis): Draw a block diagram of the universal shift register using D-type flip-flops, multiplexers, and any other logic that you may require. You can do this by hand, or using any schematic or drawing tool that you like. This is a design, not an implementation Write Verilog (in ISE) for your universal shift register. Write a Verilog testbench for your design. Simulate your design until you are convinced that it works Turn-in an annotated simulation plot (or plots) demonstrating functionality. The annotations should describe what is happening in sufficient detail to make it clear why you believe it is working.

Explanation / Answer

b.)initial
begin
     clk=1'b1;
     forever #50 clk=~clk;   
end
  
   initial
     begin
    ip = 8'b11001100;
    rst_a = 1'b1;
    load = 1'b1;
    sh_ro_lt_rt = 2'b00;
    #100;
    
    ip = 8'b10001100;
    rst_a = 1'b0;
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b11001100;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b10101101;
    
    load = 1'b1;
    sh_ro_lt_rt = 2'b01;
    #100;
    
    ip = 8'b11001101;

    load = 1'b0;
    sh_ro_lt_rt = 2'b01;
    #100;

    ip = 8'b11101100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11110000;
    load = 1'b0;
    sh_ro_lt_rt = 2'b10;
    #100;

    ip = 8'b11001100;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;

    ip = 8'b11001101;
    load = 1'b0;
    sh_ro_lt_rt = 2'b11;
    #100;
    
    ip = 8'b11001000;
    load = 1'b1;
    sh_ro_lt_rt = 2'b11;
    #100;
    $stop;
     end // initial begin
   endmodule

Related Questions

Navigate

• Browse (All)
• Browse D
• Subjects

---

---

Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.