The problem is asking you to write up the VHDL (entity and architecture parts) o
ID: 2081952 • Letter: T
Question
The problem is asking you to write up the VHDL (entity and architecture parts) of a control logic block that would drive the SEL1 and SEL0 lines of the shown diagram using the 2 bits of machine code as input. In other words, make a VHDL component that takes the machine code bits as input and outputs to the SEL lines to make the primitive microprocessor diagram work.
You are developing a primitive microprocessor with only 4 instructions: The first instruction adds two numbers presented at the two inputs. The second instruction multiplies two numbers presented at the two inputs. The third instruction adds the number presented at the first input with the result from the previous instruction. The fourth instruction multiplies the number presented at the first input with the result from the previous instruction. Assume that other mechanisms are present in the other parts of the system that take care of selecting inputs from memory and placing results in memory. See figure. Design a circuit that takes the machine code for the instructions as input and the 'sel' inputs of the two selectors as outputs, with 'sell' being the left selector controller and 'sel0' being the right selector. In other words, the key to implementing this microprocessor's instruction set is merely making sure the 'sel' lines of the selectors are working correctly. Assume that a '0' input to a 'sel' selects the top input of the selector to connect to the output, and a '1' input to a 'sel' selects the bottom input. Write out the VHDL for the entity and architecture of your design.Explanation / Answer
according to the question a 4x1 multiplexer best fits in the problem stated above which will have 2 select lines and 4 inputs and one output depending upon the select line
so assume A=first instruction
B= SECOND INSTRUCTION
C= THIRD INSTRUCTION
D=FOURTH INSTRUCTION
S=SELECT LINE (=> MACHINE CODE)
FOLLOW THE CODE BELOW:
entity PROG is
port( A,B,C,D: in std_logic;
S: in std_logic_vector(1 downto 0);
O: out std_logic);
end PROG;
Architecture behavioral of PROG is
begin
Process(S,A,B,C,D)
variable temp:std_logic;
Begin
case S is
when "00" => temp:=A;
when "01" => temp:=B;
when "10" => temp:=C;
when Others => temp:=D;
end case;
O<=temp;
end Process;
end behavioral;
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