Create a new Quartus Product project and develop the VHDL code to create the mul
ID: 2082379 • Letter: C
Question
Create a new Quartus Product project and develop the VHDL code to create the multiplexer-decoder circuit shown below. Your code should select either SWa or SWb BCD inputs and display it as a decimal number on the 7-segmeni display output. Slate a VHDL entity declaration and architecture body Use STD_LOGIC, VECTOR type to define inputs and output. You're not required to download your design onto an FPGA. You are, however, required to simulate it to show its proper operation. 1. Cover page 2. Copy and paste VHDL code (code should include comments) 3. Simulation results showing correct implementation of the circuit 4. Copy of circuitry displayed in the RTL viewerExplanation / Answer
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity test is
port (
sel : in std_logic;
sw1,sw2 :in std_logic_vector(3 downto 0);
segment7 : out std_logic_vector(6 downto 0) -- 7 bit decoded output.
);
end test;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of test is
variable bcd : std_logic_vector(7 downto 0);
begin
process (bcd)
BEGIN
if Sel = 0 then
bcd := sw1;
else
bcd := sw2;
end if
case bcd is
when "0000"=> segment7 <="0000001"; -- '0'
when "0001"=> segment7 <="1001111"; -- '1'
when "0010"=> segment7 <="0010010"; -- '2'
when "0011"=> segment7 <="0000110"; -- '3'
when "0100"=> segment7 <="1001100"; -- '4'
when "0101"=> segment7 <="0100100"; -- '5'
when "0110"=> segment7 <="0100000"; -- '6'
when "0111"=> segment7 <="0001111"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0000100"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
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