Complete the VHDL text file below for the 74LS194A universal, bi-directional shi
ID: 2082465 • Letter: C
Question
Complete the VHDL text file below for the 74LS194A universal, bi-directional shift register. Thanks in advance!
library ieee;
use ieee.std_logic_1164.all;
ENTITY q7 IS
PORT(
CLK, CLR :______________;
ABCD :_________________________;
SR,SL,S1,S0 :___________________;
Q :BUFFER _______________ (3 DOWNTO 0));
END q7;
ARCHITECTURE ______________ OF _________ IS
BEGIN
PROCESS ( )
BEGIN
IF _____________THEN
Q <= “0000”;
ELSIF CLK’EVENT AND CLK = ‘0’ THEN
IF S1 = ‘0’ AND S0 = ‘0’ THEN
Q <= Q;
ELSIF S1 = ______ AND ________ THEN
______________ <= ________________;
ELSIF S1 = _____ AND S0 = _______ THEN
______________ <= ______________;
ELSIF S1 = _________ AND S0 = _______ THEN
Q <= ABCD;
END IF;
END _________;
END _________;
END __________;
Explanation / Answer
Solution:
library ieee;
use ieee.std_logic_1164.all;
ENTITY q7 IS
PORT(
CLK, CLR : in STD_LOGIC;
ABCD : in STD_LOGIC;
SR,SL,S1,S0 : in STD_LOGIC;
Q :BUFFER out STD_LOGIC (3 DOWNTO 0));
END q7;
ARCHITECTURE SCHEMATIC OF q7 IS
BEGIN
PROCESS (CLK, CLR, Q [3:0])
BEGIN
IF CLR=’0’ THEN
Q< = “0000”;
ELSIF CLK’EVENT AND CLK = ‘0’ THEN
IF S1 = ‘0’ AND S0 = ‘0’ THEN
Q< = Q[0];
ELSIF S1 = ‘0’ AND S0 = ‘1’ THEN
Q< = Q[1];
ELSIF S1 = ‘1’ AND S0 = ‘0’ THEN
Q< = Q[2];
ELSIF S1 = ‘1’ AND S0 = ‘1’ THEN
Q< = Q[3];
ELSE Q< = ABCD;
END IF;
END PROCESS;
END SCHEMATIC;
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