Using DineroIV cache simulator, find the instruction cache misses, instruction m

Question

Using DineroIV cache simulator, find the instruction cache misses, instruction miss rate, instruction hit rate, data cache misses, data miss rate, and data hit rate for each of the two traces available in /home/rjp0109/traces and using each of the below configurations. Find the actual CPI for each trace and each configuration, if all the trace files have a miss penalty of 50 clock cycles, base CPI of 1, and has 30% load & store instructions. Use a table to show your results (total four rows and seven columns). Assume associativity as 1 (direct-mapped cache) for the data and instruction cache. A sample script file (example.sh) is given on Blackboard for one trace and one configuration.

a. L1: instruction (cache size 8K, block size 64, sub-block size 64), data (cache size 16K, block size 64, sub-block size 64)

Explanation / Answer

Dinero IV is a cache simulator for memory reference traces. It includes the following major changes over Dinero III.

1.subroutine-callable interface in addition to trace-reading program

2.simulation of multi-level caches

3.simulation of dissimilar I and D caches

4.better performance, especially for highly associative caches

5.classification of compulsory, capacity, and conflict misses

6.support for multiple input formats

Some deep-seated limitations:

1.Dinero IV is not a timing simulator. There is no notion of simulated time or cycles, only references.

2.Dinero IV is not a functional simulator. Data & instructions do not move in and out of the caches; in fact they don't exist! The primary result of simulation with Dinero IV is hit and miss information.

3.Dinero IV isn't multi-threaded. If you have a multiprocessor with enough memory, you can run multiple independent simulations concurrently.

The basic idea is to simulate a memory hierarchy consisting of various caches connected as one or more trees, with reference sources (the processors) at the leaves and a memory at each root. The various parameters of each cache can be set separately (architecture, policy, statistics). During initialization, the configuration to be simulated is built up, one cache at a time, starting with each memory as a special case. After initialization, each reference is fed to the appropriate top-level cache by a single simple function call. Lower levels of the hierarchy are handled automatically.

At some future time, Dinero IV may be extended to simulate multiprocessors. In the meantime, there is no support for consistency, so for practical purposes, the tree of caches will not be very branchy (the only time where multiple sources will feed into a cache is when separate instruction and data caches are used).

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