Design the bit serial subtractor for it signed integers which implements additio
ID: 2082849 • Letter: D
Question
Design the bit serial subtractor for it signed integers which implements addition of a 2's complement: S-A+(-B). The overflow must be detected. The datapath (Figure A) consists of two paralle shift registers SRA and SRB, an inverter for 1's complementing B a 1-bit Full Adder (FA) and D-flip-flop for carries. The least significant bits of the registers are processed, the result is loaded back to Reg A and carry bit is stored in the D-flip-flop The ASM chart (Figure B) describes operation of the control unit with input ST to startthe process, output ENABLE to enable data transfer inregisters, output LOAD to control load/shift register mode and to preset the D-flip-flop. The process completes in 5 clock periods. The system idles with S :-0 with output ENABLE 0, output LOAD is don't care. With ST 1 at the 1st clock period both outputs ENABLE and LOAD become 1, the arguments are loaded into the registers, the D-flip-flop is preset. The computed sum (S) and carry out (Cout) bits are loaded to SRA with serial input Ds and to carry D-flip-flop, respectively. In the following 4 clock periods the data bit are shifted to the right with ENABLE 1 and LOAD 0 then the system returns to the idle state. The CLEAR of the carry D-flip-flop is active-high. 1. Implement the 1-bit FA with a 3-to-8 decoder with ACTIVE-LOW outputs and two logic gates for Sum and Carry-out. Obtain the schematic with the decoder as the building block (show all inputs and outputs). 2. Implement the 4-bit shift register with enable and parallel load modes controlled by inputs E and L as follows: the register loads parallel data synchronously with clock with EL 311, shifts the data to the right with EL 10, reload the current data with EL 0x. Implement the register using D-flip-flops and any multiplexers as building blocks, obtain the schematic. 3. Implement the control unit for the datapath with any D-flip-flops and multiplexers. Perform state assignment of your choice. Obtain excitation for flip-flop inputs and draw the schematic 4. Implement the overflow detection for signed integers: obtain the schematic for circuit with output OFL to be incorporated into the subtractor (OFL-1 in the event of overflow) SRA A(3:0) NABL ENABLE. adder LOAD SRB ODI Q2 ABLE LOAD CLOCK CLOCK Figure B Figure AExplanation / Answer
At the top of the page is an interactive circuit that can compare any two 4-bit signed numbers. The circuit is also known as a 2’s complement comparator because, strictly speaking, it assumes that the numbers being compared are 2’s complement representations. Given any two 4-bit signed numbers X and Y, the circuit is able to differentiate the following relations: whether X = Y, X > Y, or X < Y.
For the most part the circuit is a 4-bit subtractor that uses the operation X – Y as the basis for comparison. The tests are simple enough. If X – Y = 0, then the two numbers must be equal. If X – Y < 0, then X must be less than Y. And if X – Y > 0, then X is greater than Y. Hence, in addition to the 4-bit subtractor, the circuit comprises some additional gates that serve to explicitly indicate the relation between the two numbers.
Using subtraction to compare two binary numbers is not difficult, as long as we look out for two particular conditions: the values of the signed bit (N) and the overflow bit (V). The signed bit is typically the output of the most significant full-adder; it indicates whether the result is positive (0) or negative (1). The overflow bit is the output signal labeled V; it indicates whether the operation results in a number that is too large (V = 1) or not (V = 0). For example, the operation (-7) – (+3) takes two 4-bit signed numbers and returns a 5-bit signed number. In decimal form (-7) – (+3) = (-7) + (-3) = -10; in binary 2’s complement form 1001 – 0011 = 1001 + 1101 = 10110.
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