Need to convert this(8 bit counter) into structual implementation. I know i will
ID: 2082897 • Letter: N
Question
Need to convert this(8 bit counter) into structual implementation. I know i will need to use an adder and mux but i am stuck on how to proceed.
`timescale 1ns / 1ps
module Count8(clk,rst,pause,up,count7);
input clk, rst, pause,up;
output [7:0] count7; // this is how you declare an 8 bit signal initial Verilog
reg [7:0] count7;
parameter S_0= 8'b00000000,
//the values 1-58 could be displayed here but will not be called so they were not set to a different variable
S_59=8'b00111011;
//state register
//If Reset is 1, the counter should reset its count value to zero (0000).
//If Reset is 0 and Pause is 1, the counter should pause and continue displaying the current count value.
//If Up is 1, on every clock cycle the counter should count up by one number.
//If Up is 0, the counter should count down on every clock cycle.
always @(posedge clk or posedge rst) begin
if (rst==1) // initial state
count7 <= S_0;
else
if(pause==1)
count7 <= count7;
else
if (up==1)
if(count7 < S_59)
count7 <= count7 +1;
else
count7 <= S_0;
else
if(count7 == S_0)
count7 <= S_59;
else
count7 <= count7 -1;
end
endmodule
Explanation / Answer
EXAMPLE:
`timescale 10ns/1ns
module tim();
reg i;
initial
begin
i=0;
#7.7212;
i=1;
$display("STATEMENT 1 :: time is ",$stime);
#7.123;
$finish;
end
endmodule
module try;
time delay_time = 7.721;
initial begin
$display("STATEMENT 2 :: delay for %0t",delay_time );
end
endmodule
RESULTS:
STATEMENT 1 :: time is 8
STATEMENT 2 :: delay for 80
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