Problem 1. Figure 12–76 shows a VHDL program that uses state machine design to c
ID: 2083110 • Letter: P
Question
Problem 1. Figure 12–76 shows a VHDL program that uses state machine design to create a Gray code counter. The VHDL code is shown here.
LIBRARY ieee; -------------------------------------
USE ieee.std_logic_1164.ALL; -- State Machine Gray Code Counter --
-------------------------------------
ENTITY state_gray IS
PORT(clk : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(2 downto 0));
END state_gray ;
ARCHITECTURE arc OF state_gray IS
TYPE state_type IS (s0, s1, s2, s3, s4, s5, s6, s7);
SIGNAL state: state_type;
BEGIN
PROCESS (clk)
BEGIN
IF clk'EVENT AND clk = '1' THEN
CASE state IS
WHEN s0 => state <= s1;
WHEN s1 => state <= s2;
WHEN s2 => state <= s3;
WHEN s3 => state <= s4;
WHEN s4 => state <= s5;
WHEN s5 => state <= s6;
WHEN s6 => state <= s7;
WHEN s7 => state <= s0;
END CASE;
END IF;
END PROCESS;
WITH state SELECT
q <= "000" WHEN s0,
"001" WHEN s1,
"011" WHEN s2,
"010" WHEN s3,
"110" WHEN s4,
"111" WHEN s5,
"101" WHEN s6,
"100" WHEN s7;
END arc;
Use a technique similar to the one presented to develop a sequencer that counts up for just the odd single digit numbers (1–3–5–7–9–1–, etc.). Add a direction control input so that the user can change from an odd up-counter to an odd down-counter. Develop a simulation file to demonstrate its operation.
Explanation / Answer
The code for the bidirectional odd counter on the lines of the given gray code counter is as follows:
The names of the variables and functions is similar to one given in the code in the question for the sake of simplicity. Only the application is altered.
------code:
library IEEE;
use IEEE.std_logic_1164.all;
entity odd_counter is
port(clk, direction: in std_logic;
q: out std_logic_vector(3 downto 0));
end odd_counter;
architecture arc of odd_counter is
type state_type is(s0, s1, s2, s3, s4);
signal state: state_type;
begin
process(direction, clk)
begin
if clk'event and clk = '1'
if direction = '0' then
case state is
when s0 =>
state <= s1;
when s1 =>
state <= s2;
when s2 =>
state <= s3;
when s3 =>
state <= s4;
when s4 =>
state <= s0;
end case;
else
case state is
when s0 =>
state <= s4;
when s1 =>
state <= s0;
when s2 =>
state <= s1;
when s3 =>
state <= s2;
when s4 =>
state <= s3;
end case;
end if;
end process;
with state select
q <= "0001";
when s0,
"0011"
when s1,
"0101"
when s2,
"0111"
when s3,
"1001"
when s4;
end arc;
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