Write a VHDL model and simulate an 8-bit adder/subtractor unit with overflow det

Question

Write a VHDL model and simulate an 8-bit adder/subtractor unit with overflow detection using three 4-bit carry select adders. Each carry select adder stage must be designed using carry-lookahead adder for faster performance.

Explanation / Answer

library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity adder8bit is Port ( a : in STD_LOGIC_VECTOR (7 downto 0); b : in STD_LOGIC_VECTOR (7 downto 0); cin : in STD_LOGIC; o : out STD_LOGIC_VECTOR (7 downto 0); cout : out STD_LOGIC); end adder8bit; architecture Behavioral of adder8bit is component fulladder is Port ( a : in STD_LOGIC; b : in STD_LOGIC; cin : in STD_LOGIC; o : out STD_LOGIC; cout : out STD_LOGIC); end component; signal t1,t2:std_logic:='0'; begin C1: fulladder port map( a => a(0), b => b(0), cin => cin, o => o(0), cout => t1 ); C2: fulladder port map( a => a(1), b => b(1), cin => t1, o => o(1), cout => t2 ); C3: fulladder port map( a => a(2), b => b(2), cin => t2, o => o(2), cout => t1 ); C4: fulladder port map( a => a(3), b => b(3), cin => t1, o => o(3), cout => t2 ); C5: fulladder port map( a => a(4), b => b(4), cin => t2, o => o(4), cout => t1 ); C6: fulladder port map( a => a(5), b => b(5), cin => t1, o => o(5), cout => t2 ); C7: fulladder port map( a => a(6), b => b(6), cin => t2, o => o(6), cout => t1 ); C8: fulladder port map( a => a(7), b => b(7), cin => t1, o => o(7), cout => cout ); end Behavioral;

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