Digital Electronics: Please don\'t write the code with an advanced way that I di
ID: 2083665 • Letter: D
Question
Digital Electronics:
Please don't write the code with an advanced way that I didn't learn yet in the class.
Thank you for your help!
Design and simulate a 4-bit up-down counter with parallel load and synchronous clear. The counter has four control inputs load, clear, up and down. The order of precedence is clear, load, up and down. Develop the function table for this counter and write the Verilog behavioral code to implement this counter. data L cnto data cnt1 data2 cnt2 data3 cnt3 Four bit up/down up Counter down load clear clockExplanation / Answer
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity updown_counter is
port( data: in std_logic_vector(0 to 3);
clock: in std_logic;
clear: in std_logic;
load: in std_logic;
up: in std_logic;
down: in std_logic;
cnt: out std_logic_vector(0 to 3)
);
end updown_counter;
architecture my_behav of updown_counter is
signal temp: std_logic_vector(0 to 3);
begin
process(clock,clear)
begin
if clear='1' then
temp<= "0000";
elsif (clock'event and clock='1') then
if load='1' then
temp<=data;
elsif (load='0' and up='1') then
temp<=temp+1;
elsif (load='0' and down='1') then
temp<=temp-1;
end if;
end if;
end process;
cnt<=temp;
end my_behav;
Related Questions
drjack9650@gmail.com
Navigate
Integrity-first tutoring: explanations and feedback only — we do not complete graded work. Learn more.